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SST28SF040A-150-4C-NH 供应信息 IC Datasheet 数据表 (3/24 页)
按型号查询：
SST28SF040A-150-4C-NH
4兆位（ 512K ×8 ）超快闪EEPROM
[4 Mbit (512K x8) SuperFlash EEPROM]
&&SST28SF040A-150-4C-NHPDF文件：
4兆位（ 512K ×8 ）超快闪EEPROM[4 Mbit (512K x8) SuperFlash EEPROM]
文件大小：&&321 KPDF页数：
&&24 页联系供应商：&& 品牌Logo:
&&&&SST [ SILICON STORAGE TECHNOLOGY, INC ]
4 Mbit SuperFlash EEPROMSST28SF040A / SST28VF040AData SheetThe Read operation of the SST28SF/VF040A are con-trolled by OE# and CE# at logic low. When CE # is high,the chip is deselected and only standby power will be con-sumed. OE# is the output control and is used to gate datafrom the output pins. The data bus is in high impedancestate when CE# or OE# are high.rising edge of OE# or CE#, whichever occurs first. A similarseven read sequence of 1823H, 1820H, 1822H, 0418H,041BH, 0419H, 040AH will protect the device. Also refer toFigures 10 and 11 for the 7 read cycle sequence SoftwareData Protection. The I/O pins can be in any state (i.e., high,low, or tri-state).Read-ID operationThe Read-ID operation is initiated by writing a single com-mand (90H). A read of address 0000H will output the man-ufacturer’s ID (BFH). A read of address 0001H will outputthe device ID (04H). Any other valid command will termi-nate this operation.Write Operation Status DetectionThe SST28SF/VF040A provide three means to detect thecompletion of a Write operation, in order to optimize thesystem Write operation. The end of a Write operation(Erase or Program) can be detected by three means: 1)monitoring the Data# Polling bit, 2) monitoring the Togglebit, or 3) by two successive reads of the same data. Thesethree detection mechanisms are described below.The actual completion of the nonvolatile Write is asynchro- therefore, either a Data# Polling orToggle Bit read may be simultaneous with the completionof the Write cycle. If this occurs, the system may possiblyget an erroneous result, i.e., valid data may appear to con-flict with the DQ used. In order to prevent spurious rejec-tion, if an erroneous result occurs, the software routineshould include a loop to read the accessed location anadditional two (2) times. If both reads are valid, then thedevice has completed the Write cycle, otherwise the rejec-tion is valid.Data ProtectionIn order to protect the integrity of nonvolatile data storage,the SST28SF/VF040A provide bothhardware and software features to prevent inadvertentwrites to the device, for example, during system power-upor power-down. Such provisions are described below.Hardware Data ProtectionThe SST28SF/VF040A are designed with hardware fea-tures to prevent inadvertent writes. This is done in the fol-lowing ways:1. Write Cycle Inhibit Mode: OE# low, CE#, or WE#high will inhibit the Write operation.2. Noise/Glitch Protection: A WE# pulse width of lessthan 5 ns will not initiate a Write cycle.3. VDDPower Up/Down Detection: The Write opera-tion is inhibited when VDDis less than 2.0V.4. After power-up, the device is in the Read modeand the device is in the Software Data Protectstate.Data# Polling (DQ7)The SST28SF/VF040A feature Data# Polling to indicatethe Write operation status. During a Write operation, anyattempt to read the last byte loaded during the byte-loadcycle will receive the complement of the true data on DQ7.Once the Write cycle is completed, DQ7will show truedata. The device is then ready for the next operation. SeeData# Polling to function correctly, the byte being polledmust be erased prior to programming.Software Data Protection (SDP)The SST28SF/VF040A have software methods to furtherprevent inadvertent writes. In order to perform an Erase orProgram operation, a two-step command sequence con-sisting of a set-up command followed by an execute com-mand avoids inadvertent erasing and programming of thedevice.The SST28SF/VF040A will default to Software Data Pro-tection after power up. A sequence of seven consecutivereads at specific addresses will unprotect the device Theaddress sequence is 1823H, 1820H, 1822H, 0418H,041BH, 0419H, 041AH. The address bus is latched on the(C)2001 Silicon Storage Technology, Inc.Toggle Bit (DQ6)An alternative means for determining the Write operationstatus is by monitoring the Toggle Bit, DQ6. During a Writeoperation, consecutive attempts to read data from thedevice will result in DQ6toggling between logic 0 (low) andlogic 1 (high). When the Write cycle is completed, the tog-gling will stop. The device is then ready for the next opera-tion. See Figure 13 for Toggle Bit timing waveforms.S 6/013103SST28SF040A-90-4C-NH
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