From Wikipedia, the free encyclopedia
Microcode is "a technique that imposes an interpreter between the hardware and the architectural level of a computer". As such, the microcode is a layer of hardware-level instructions that implement higher-level
instructions or internal
sequencing in many
elements. Microcode is used in general-purpose , as well as in more specialized processors such as , , , , , , , and in other hardware.
Microcode typically resides in special high-speed memory and translates machine instructions,
data or other input into sequences of detailed circuit-level operations. It separates the machine instructions from the underlying
so that instructions can be designed and altered more freely. It also facilitates the building of complex multi-step instructions, while reducing the complexity of computer circuits. Writing microcode is often called microprogramming and the microcode in a particular processor implementation is sometimes called a microprogram.
More extensive microcoding allows small and simple
more powerful architectures with wider , more
and so on, which is a relatively simple way to achieve software compatibility between different products in a processor family.
Some hardware vendors, especially , use the term microcode as a synonym for . In that way, all code within a device is termed microcode regardless of it for example,
are said to have their microcode updated, though they typically contain both microcode and firmware.
When compared to normal application programs, the elements composing a microprogram exist on a lower conceptual level. To avoid confusion, each microprogram-related element is differentiated by the micro prefix: microinstruction, microassembler, microprogrammer, , etc.
Engineers normally write the microcode during the design phase of a processor, storing it in a
(PLA) structure, or in a combination of both. However, machines also exist that have some or all microcode stored in
or . This is traditionally denoted as writeable
in the context of computers, which can be either read-only or . In the latter case, the CPU initialization process loads microcode into the control store from another storage medium, with the possibility of altering the microcode to correct bugs in the instruction set, or to implement new machine instructions.
Complex digital processors may also employ more than one (possibly microcode-based)
in order to delegate sub-tasks that must be performed essentially asynchronously in parallel. A high-level programmer, or even an
programmer, does not normally see or change microcode. Unlike machine code, which often retains some
among different processors in a family, microcode only runs on the exact
for which it is designed, as it constitutes an inherent part of the particular processor design itself.
Microprograms consist of series of microinstructions, which control the CPU at a very fundamental level of hardware circuitry. For example, a single typical horizontal microinstruction might specify the following operations:
Connect register 1 to the A side of the
Connect register 7 to the B side of the ALU
Set the ALU to perform
Set the ALU's carry input to zero
Store the result value in register 8
Update the condition codes from the ALU status flags (negative, zero, overflow, and carry)
Microjump to micro nnn for the next microinstruction
To simultaneously control all processor's features in one cycle, the microinstruction is often wider than 50 e.g., 128 bits on a 360/85 with an emulator feature. Microprograms are carefully designed and optimized for the fastest possible execution, as a slow microprogram would result in a slow machine instruction and degraded performance for related application programs that use such instructions.
Microcode was originally developed as a simpler method of developing the control logic for a computer. Initially, CPU
were . Each step needed to fetch, decode, and execute the machine instructions (including any operand address calculations, reads, and writes) was controlled directly by
and rather minimal
state machine circuitry. While very efficient, the need for powerful instruction sets with multi-step addressing and complex operations (see below) made such hard-wired processors difficult highly encoded and varied-length instructions can contribute to this as well, especially when very irregular encodings are used.
Microcode simplified the job by allowing much of the processor's behaviour and programming model to be defined via microprogram routines rather than by dedicated circuitry. Even late in the design process, microcode could easily be changed, whereas hard-wired CPU designs were very cumbersome to change. Thus, this greatly facilitated CPU design.
From the 1940s to the late 1970s, a large portion of prog higher-level instructions mean greater programmer productivity, so an important advantage of microcode was the relative ease by which powerful machine instructions can be defined. The ultimate extension of this are "Directly Executable High Level Language" designs, in which each statement of a high-level language such as
is entirely and directly executed by microcode, without compilation. The
Fountainhead Processor are examples of this. During the 1970s, CPU speeds grew more quickly than memory speeds and numerous techniques such as ,
were used to alleviate this. High-level machine instructions, made possible by microcode, helped further, as fewer more complex machine instructions require less memory bandwidth. For example, an operation on a character string can be done as a single machine instruction, thus avoiding multiple instruction fetches.
Architectures with instruction sets implemented by complex microprograms included the
. The approach of increasingly complex microcode-implemented instruction sets was later called . An alternate approach, used in many , is to use
(instead of combinational logic) mainly for instruction decoding, and let a simple state machine (without much, or any, microcode) do most of the sequencing. The
is an example of a microprocessor using a PLA for instruction decode and sequencing. The PLA is visible in photomicrographs of the chip, and its operation can be seen in the transistor-level simulation.
Microprogramming is still used in modern CPU designs. In some cases, after the microcode is debugged in simulation, logic functions are substituted for the control store.[] Logic functions are often faster and less expensive than the equivalent microprogram memory.
A processor's microprograms operate on a more primitive, totally different, and much more hardware-oriented architecture than the assembly instructions visible to normal programmers. In coordination with the hardware, the microcode implements the programmer-visible architecture. The underlying hardware need not have a fixed relationship to the visible architecture. This makes it easier to implement a given instruction set architecture on a wide variety of underlying hardware micro-architectures.
The IBM System/360 has a 32-bit architecture with 16 general-purpose registers, but most of the System/360 implementations actually use hardware that implemented a much simpler underlyi for example, the
has 8-bit data paths to the arithmetic logic unit (ALU) and main memory and implemented the general-purpose registers in a special unit of higher-speed , and the
has 8-bit data paths to the ALU and 16-bit data paths to main memory and also implemented the general-purpose registers in a special unit of higher-speed core memory. The
has full 32-bit data paths and implements the general-purpose registers in a special unit of higher-speed core memory. The Model 65 through the Model 195 have larger data paths and implement the general-purpose registers in faster transistor circuits.[] In this way, microprogramming enabled IBM to design many System/360 models with substantially different hardware and spanning a wide range of cost and performance, while making them all architecturally compatible. This dramatically reduces the number of unique system software programs that must be written for each model.
A similar approach was used by Digital Equipment Corporation (DEC) in their VAX family of computers. As a result, different VAX processors use different microarchitectures, yet the programmer-visible architecture does not change.
Microprogramming also reduces the cost of field changes to correct defects () a bug can often be fixed by replacing a portion of the microprogram rather than by changes being made to
and wiring.
In 1947, the design of the
introduced the concept of a control store as a way to simplify computer design and move beyond
methods. The control store is a : a two-dimensional lattice, where one dimension accepts "control time pulses" from the CPU's internal clock, and the other connects to control signals on gates and other circuits. A "pulse distributor" takes the pulses generated by the CPU clock and breaks them up into eight separate time pulses, each of which activates a different row of the lattice. When the row is activated, it activates the control signals connected to it.
Described another way, the signals transmitted by the control store are being played much like a
roll. That is, they are controlled by a sequence of very wide words constructed of , and they are "played" sequentially. In a control store, however, the "song" is short and repeated continuously.
enhanced this concept by adding conditional execution, a concept akin to a
in computer software. His initial implementation consisted of a pair of matrices: the first one generated signals in the manner of the Whirlwind control store, while the second matrix selected which row of signals (the microprogram instruction word, so to speak) to invoke on the next cycle. Conditionals were implemented by providing a way that a single line in the control store could choose from alternatives in the second matrix. This made the control signals conditional on the detected internal signal. Wilkes coined the term microprogramming to describe this feature and distinguish it from a simple control store.
BIOS showing a " CPU uCode Loading Error" after a failed attempt to upload microcode patches into the CPU.
In common with many other complex mechanical devices,
uses banks of
to control each operation. That is, it has a read-only control store. As such, it deserves to be recognised as the first microprogrammed computer to be designed, although it had not been implemented in hardware until 2002.
reputedly uses a hard-wired control store consisting of wires threaded through ferrite cores, known as "the laces".
Most models of the IBM System/360 series are microprogrammed:
is unique among System/360 models in using the top 16 K bytes of core storage to hold the control storage for the microprogram. The 2025 uses a 16-bit microarchitecture with seven control words (or microinstructions). At power up, or full system reset, the microcode is loaded from the card reader. The
emulation for this model is loaded this way.
The , the slowest model in the line, uses an 8-bit microarchitecture with only a fe everything that the programmer saw is emulated by the microprogram. The microcode for this model is also held on special punched cards, which are stored inside the machine in a dedicated reader per card, called "CROS" units (Capacitor Read-Only Storage). A second CROS reader is installed for machines ordered with 1620 emulation.
uses 56-bit control words. The 2040 box implements both the System/360 main processor and the multiplex channel (the I/O processor). This model uses "TROS" dedicated readers similar to "CROS" units, but with an inductive pickup (Transformer Read-only Store).
has two internal datapaths which operated in parallel: a 32-bit datapath used for arithmetic operations, and an 8-bit data path used in some logical operations. The control store uses 90-bit microinstructions.
has separate instruction fetch (I-unit) and execution (E-unit) to provide high performance. The I-unit is hardware controlled. The E-uni the control words are 108 bits wide on a basic 360/85 and wider if an emulator feature is installed.
is microprogrammed with hand wired ferrite cores (a ) pulsed by a sequencer with conditional execution. Wires routed through the cores are enabled for various data and logic elements in the processor.
The Digital Equipment Corporation
processors, with the exception of the PDP-11/20, are microprogrammed.
minicomputers are microprogrammed. The task of writing microcode for the
is detailed in the Pulitzer Prize-winning book titled .
Many systems from
are microprogrammed:
The B700 "microprocessor" execute application-level opcodes using sequences of 16-bit microinstructions s each of these is either a register-load operation or mapped to a single 56-bit "nanocode" instruction stored in read-only memory. This allows comparatively simple hardware to act either as a mainframe peripheral controller or to be packaged as a standalone computer.
is implemented with radically different hardware including bit-addressable main memory but has a similar multi-layer organisation. The operating system preloads the interpreter for whatever language is required. These interpreters present different virtual machines for , , etc.
produced computers in which the microcode is ac this allows the creation of custom assembler level instructions. Microdata's
operating system design makes extensive use of this capability.
(RCP), which serves as the console's
and audio processor, it is possible to implement new effects or tweak the processor to achieve the desired output. Some notable examples of custom RCP microcode include the high-resolution graphics, particle engines, and unlimited draw distances found in 's , , and ; and the
playback found in Angel Studios' .
The VU0 and VU1 vector units in the
a in fact, VU1 is only accessible via microcode for the first several generations of the SDK.
The MicroCore Labs
are examples of highly encoded "vertical" microsequencer implementations of the Intel
and the Intel 8051.
Each microinstruction in a microprogram provides the bits that control the functional elements that internally compose a CPU. The advantage over a hard-wired CPU is that internal CPU control becomes a specialized form of a computer program. Microcode thus transforms a complex electronic design challenge (the control of a CPU) into a less complex programming challenge. To take advantage of this, a CPU is divided into several parts:
picks the next word of the control store. A sequencer is mostly a counter, but usually also has some way to jump to a different part of the control store depending on some data, usually data from the
and always some part of the control store. The simplest sequencer is just a register loaded from a few bits of the control store.
set is a fast memory containing the data of the central processing unit. It may include the program counter, stack pointer, and other numbers that are not easily accessible to the application programmer. Often the register set is a triple- that is, two registers can be read, and a third written at the same time.
performs calculations, usually addition, logical negation, a right shift, and logical AND. It often performs other functions, as well.
There may also be a
and a , used to access the main . Together, these elements form an "". Most modern
have several execution units. Even simple computers usually have one unit to read and write memory, and another to execute user code. These elements could often be brought together as a single chip. This chip comes in a fixed width that would form a "slice" through the execution unit. These are known as "" chips. The
family is one of the best known examples of bit slice elements. The parts of the execution units and the execution units themselves are interconnected by a bundle of wires called a .
Programmers develop microprograms, using basic software tools. A
allows a programmer to define the table of bits symbolically. Because of its close relationship to the underlying architecture, "microcode has several properties that make it difficult to generate using a compiler." A
program is intended to execute the bits in the same way as the electronics, and allows much more freedom to debug the microprogram. After the microprogram is finalized, and extensively tested, it is sometimes used as the input to a computer program that constructs logic to produce the same data. This program is similar to those used to optimize a . No known computer program can produce optimal logic, but even good logic can vastly reduce the number of transistors from the number required for a ROM control store. This reduces the cost of producing, and the electricity consumed by, a CPU.
Microcode can be characterized as horizontal or vertical, referring primarily to whether each microinstruction controls CPU elements with little or no decoding (horizontal microcode) or requires extensive decoding by
before doing so (vertical microcode). Consequently, each horizontal microinstruction is wider (contains more bits) and occupies more storage space than a vertical microinstruction.
"Horizontal microcode has several discrete micro-operations that are combined in a single microinstruction for simultaneous operation." Horizontal microcode is typically contained in a fairl it is not uncommon for each word to be 108 bits or more. On each tick of a sequencer clock a microcode word is read, decoded, and used to control the functional elements that make up the CPU.
In a typical implementation a horizontal microprogram word comprises fairly tightly defined groups of bits. For example, one simple arrangement might be:
Register source A
Register source B
Destination register
Type of jump
Jump address
For this type of micromachine to implement a JUMP instruction with the address following the opcode, the microcode might require two clock ticks. The engineer designing it would write microassembler source code looking something like this:
# Any line starting with a number-sign is a comment
# This is just a label, the ordinary way assemblers symbolically represent a
# memory address.
InstructionJUMP:
# To prepare for the next instruction, the instruction-decode microcode has already
# moved the program counter to the memory address register. This instruction fetches
# the target address of the jump instruction from the memory word following the
# jump opcode, by copying from the memory data register to the memory address register.
# This gives the memory system two clock ticks to fetch the next
# instruction to the memory data register for use by the instruction decode.
# The sequencer instruction "next" means just add 1 to the control word address.
MDR, NONE, MAR,
COPY, NEXT, NONE
# This places the address of the next instruction into the PC.
# This gives the memory system a clock tick to finish the fetch started on the
# previous microinstruction.
# The sequencer instruction is to jump to the start of the instruction decode.
MAR, 1, PC, ADD,
InstructionDecode
# The instruction decode is not shown, because it is usually a mess, very particular
# to the exact processor being emulated. Even this example is simplified.
# Many CPUs have several ways to calculate the address, rather than just fetching
# it from the word following the op-code. Therefore, rather than just one
# jump instruction, those CPUs have a family of related jump instructions.
For each tick it is common to find that only some portions of the CPU are used, with the remaining groups of bits in the microinstruction being no-ops. With careful design of hardware and microcode, this property can be exploited to parallelise operations that use different areas of the CPU; for example, in the case above, the ALU is not required during the first tick, so it could potentially be used to complete an earlier arithmetic instruction.
In vertical microcode, each microinstruction is significantly encoded –
that is, the bit fields generally pass through intermediate combinatory logic that, in turn, generates the actual control and sequencing signals for internal CPU elements (ALU, registers, etc.). This is in contrast with horizontal microcode, in which the bit fields themselves either directly produce the control and sequencing signals or are only minimally encoded. Consequently, vertical microcode requires smaller instruction lengths and less storage, but requires more time to decode, resulting in a slower CPU clock.
Some vertical microcode is just the assembly language of a simple conventional computer that is emulating a more complex computer. Some processors, such as
processors and the CMOS microprocessors on later IBM
mainframes and
mainframes, have
(the term used on Alpha processors) or
(the term used on IBM mainframe microprocessors). This is a form of machine code, with access to special registers and other hardware resources not available to regular machine code, used to implement some instructions and other functions, such as page table walks on Alpha processors.
Another form of vertical microcode has two fields:
Field select
Field value
The field select selects which part of the CPU will be controlled by this word of the control store. The field value actually controls that part of the CPU. With this type of microcode, a designer explicitly chooses to make a slower CPU to save money by reducing the unused bits
however, the reduced complexity may increase the CPU's clock frequency, which lessens the effect of an increased number of cycles per instruction.
As transistors became cheaper, horizontal microcode came to dominate the design of CPUs using microcode, with vertical microcode being used less often.
When both vertical and horizontal microcode are used, the horizontal microcode may be referred to as nanocode or picocode.
Writable control store[]
A few computers were built using "writable microcode". In this design, rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called a writable control store or WCS. Such a computer is sometimes called a writable instruction set computer or WISC.
Many experimental prototype computers use wri there are also commercial machines that use writable microcode, such as the , early
workstations, the
8800 ("Nautilus") family, the
L- and G-machines, a number of IBM System/360 and
implementations, some DEC
machines, and the .
Many more machines offer user-programmable writable control stores as an option, including the , DEC
V-70 series . The IBM System/370 includes a facility called Initial-Microprogram Load (IML or IMPL) that can be invoked from the console, as part of
(POR) or from another processor in a
Some commercial machines, for example IBM 360/85, have both a read-only storage and a writable control store for microcode.
WCS offers several advantages including the ease of patching the microprogram and, for certain hardware generations, faster access than ROMs can provide. User-programmable WCS allows the user to optimize the machine for specific purposes.
Starting with the
in 1995, several Intel
CPUs have writable microcode. This, for example, has allowed bugs in the
microcodes to be fixed by patching their microprograms, rather than requiring the entire chips to be replaced.
The design trend toward heavily microcoded processors with complex instructions began in the early 1960s and continued until roughly the mid-1980s. At that point the
design philosophy started becoming more prominent.
A CPU that uses microcode generally takes several clock cycles to execute a single instruction, one clock cycle for each step in the microprogram for that instruction. Some
processors include instructions that can take a very long time to execute. Such variations interfere with both
and, what is far more important in modern systems, .
When designing a new processor, a
RISC has the following advantages over microcoded CISC:
Programming has largely moved away from assembly level, so it's no longer worthwhile to provide complex instructions for productivity reasons.
Simpler instruction sets allow direct execution by hardware, avoiding the performance penalty of microcoded execution.
Analysis shows complex instructions are rarely used, hence the machine resources devoted to them are largely wasted.
The machine resources devoted to rarely used complex instructions are better used for expediting performance of simpler, commonly used instructions.
Complex microcoded instructions may require many clock cycles that vary, and are difficult to
for increased performance.
There are counterpoints as well:
The complex instructions in heavily microcoded implementations may not take much extra machine resources, except for microcode space. For instance, the same ALU is often used to calculate an effective address as well as computing the result from the actual operands (e.g., the original , , and others).
The simpler non-RISC instructions (i.e., involving direct memory ) are frequently used by modern compilers. Even immediate to stack (i.e., memory result) arithmetic operations are commonly employed. Although such memory operations, often with varying length encodings, are more difficult to pipeline, it is still fully feasible to do so - clearly exemplified by the , , , , etc.
Non-RISC instructions inherently perform more work per instruction (on average), and are also normally highly encoded, so they enable smaller overall size of the same program, and thus better use of limited cache memories.
Modern CISC/RISC implementations (e.g., x86 designs) decode instructions into dynamically buffered
with instruction encodings similar to traditional fixed microcode. Ordinary static microcode is used as hardware assistance for complex multistep operations such as auto-repeating instructi it is also used for special purpose instructions (such as ) and internal control and configuration purposes.
The simpler instructions in CISC architectures are also directly executed in hardware in modern implementations.
Many RISC and
processors are designed to execute every instruction (as long as it is in the cache) in a single cycle. This is very similar to the way CPUs with microcode execute one microinstruction per cycle. VLIW processors have instructions that behave similarly to very wide horizontal microcode, although typically without such fine-grained control over the hardware as provided by microcode. RISC instructions are sometimes similar to the narrow vertical microcode.
Microcoding has been popular in application-specific processors such as .
IBM horizontally microcoded processors had multiple micro-orders and register select fields that required decoding
Kent, A Williams, James G. (April 5, 1993). . New York: Marcel Dekker, Inc.   2016.
Manning, B.M.; Mitby, J.S; Nicholson, J.O. (November 1979). . IBM Technical Disclosure Bulletin. 22 (6).
Often denoted a ROM/PLA control store in the context of usage in a CPU; .
(PDF). . 1967. p. 7 2011.
Everett, R.R. & Swain, F.E. (1947).
(PDF). Report R-127. MIT Servomechanisms Laboratory 2006.
. Emidec.org.uk 2010.
Daniel P. Siewiorek, ,
(1982). Computer Structures: Principles and Examples. : .  .
. IGN64. November 10, .
. IGN. December 12, .
Meynink, Todd (July 28, 2000). . .
Neal H Andy Gimblett (). . mat.uson.mx.
(PDF). . May .
Robert Vaupel. .  .
Rogers, Bob (Sep–Oct 2012). . IBM Systems Magazine.
Spruth, Wilhelm (Dec 2012). . Springer Science & Business Media. p. 31.   2015.
article by Philip Koopman Jr. 1987
Mark Smotherman. . 4096 x 75-bit SRAM writeable control store: 74-bit microinstruction with 1 parity bit (18 fields)
(PDF). Fourth Edition. IBM. September 1974. pp. 98, 245. GA22-7000-4.
(PDF). SECOND EDITION. IBM. June 1968. A22-6916-1.
IBM System/360 Special Feature Description 709/ Compatibility Feature for IBM System/360 Model 85. First Edition. IBM. March 1969. GA27-2733-0.
Stiller, A Paul, Matthias (). . . Trends & News (in German). .
from the original on .
, chapter 9.11: "Microcode update facilities", December 2009.
Smith, Richard E. (1988). . Annals of the History of Computing. 10 (4): 277–303. : 2006.
Smotherman, Mark (2005).
(1986). . Annals of the History of Computing. 8 (2): 116–126. : 2006.
(April 1953). . Proc. Cambridge Phil. Soc. 49 (pt. 2): 230–238. : 2006.
Husson, S.S (1970). Microprogramming Principles and Practices. Prentice-Hall.  .
Tucker, S. G.,
IBM Systems Journal, Volume 6, Number 4, pp. 222–241 (1967)
in Wiktionary, the free dictionary.
This article's use of
may not follow Wikipedia's policies or guidelines. Please
by removing
external links, and converting useful links where appropriate into . (February 2017) ()
(fixes the issues when running 32-bit virtual machines in PAE mode)
, March 2013, by Ben Hawkes, archived from the original on September 7, 2015
, , 2002, by Alexander Wolfe, archived from the original on March 9, 2003
, July 26, 2004
: Hidden categories: